Re: Misc: BGBCC targeting RV64G, initial results...

On Fri, 27 Sep 2024 21:28:41 +0000, BGB wrote:

On 9/27/2024 10:52 AM, MitchAlsup1 wrote:

My 66000 can do::  1 < i && i <= MAX in 1 instruction
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>
BJX2:
   CMPQGT R4, 1, R16
   CMPQLT R4, (MAX+1), R17 //*1
   AND    R16, R17, R5
>
So, more than 1 instruction, but less than faking it with SLT / SLTI ...
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     CMP    Rt,Ri,MAX
     BFIN   Rt,label       // fin = Fortran IN
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It is better for performance though to be able to flip the output bit in
the pipeline than to need to use an XOR instruction or similar.

I do integer negation by flipping all the bits and running a carry
into the subsequent ALU.
Thus, if the target calculation unit is logical, one gets inversion
integer gets negation, and FPUs only invert the sign bit.