Re: Misc: BGBCC targeting RV64G, initial results...

On Mon, 30 Sep 2024 2:19:41 +0000, BGB wrote:

On 9/29/2024 2:11 PM, MitchAlsup1 wrote:

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I noticed this in 1991 when we got Mc88120 simulator up and running.
GBOoO chips are <nearly> best served when there is the smallest number
of instructions.

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Looking it up, seems the CPU in question (MIPS R4300) was:
   16K L1 I$ cache;
   8K L1 D$ cache;
   No L2 cache (but could be supported off-die);
   1-wide scalar, 32 or 64 bit
   Non pipelined FPU and multiplie

we had::
16 KB 4-way banked unified cache
and a 1024 entry trace cache
Best case DRAM was 5 cycles with typical case at 9 cycles

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How many bits does one of these jumbo prefixes consume ?

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The prefix itself is 32 bits.
   In the context of XG3, it supplies 23 or 27 bits.

So it has a cost of 9 or 5 bits
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Well, and people obsessing on what happens if an interrupt somehow
occurs "between" the prefix and prefixed instruction.
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Which, as I have tended to implement them, is simply not possible, since
everything is fetched and decoded at the same time.
>
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Granted, yes, it does add the drawback of needing to have tag-bits to
remember the mode, and maybe the CPU hiding mode bits in the high order
bits of the link register and similar is not such an elegant idea.

So, what do you do when the jumbo is in the last word of a line and
the next line takes "a long time" to arrive ?
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For your implementation, yes. For all others:: <at best> maybe.

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Maybe.
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I could maybe consider widening fetch/decode to 128-bits if there were a
compelling use case.

Remember I am doing 128-bit fetches on a 1-wide machine
and 3 128-bit fetches on the 6-wide machine.