Re: is Vax addressing sane today

On Sat, 5 Oct 2024 15:06:39 +0000, Scott Lurndal wrote:

"Paul A. Clayton" <paaronclayton@gmail.com> writes:

On 10/4/24 7:30 PM, Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Fri, 4 Oct 2024 7:05:34 +0000, Anton Ertl wrote:
>

George Neuner <gneuner2@comcast.net> writes:

<snipping>

>

>
My 66000 has a MemMove instruction consisting of a 1 word instruction,
that leaves DECODE and enters into one MEMory unit, where it proceeds
to AGEN and Read, AGEN and Write, leaving the rest of the function
units proceeding to whatever is next.
>
One thing I did different, here, none of the 3 registers is modified,
yet I retain the ability to take exception and re-play the instruction
from where it left off {in state never visible to the instruction
stream except via DECODE stage.}

>
What happens if the exception handler reschedules the CPU to
a different task before returning from the exception?

>
I ass-me that like the PREDicate instruction modifier, there is
_implicit_ state that is saved on context switches. I.e., there is
extra storage space in the context store for such data.
>
My 66000 uses hardware context saving, so software can be ignorant
of such (aside from reserving enough storage).

>
I got the impression that it wasn't so much context saving,
as context switching (i.e. storage per 'process/thread');

Thread headers and thread register files are treated as
a write back cache. Core knows where it originally
got the RF and thus remembers where to put it back.
This state area is in the thread control block. So, there
is no way it can "not be there". An OS will not start a
process until there is enough memory to contain all
thread state {and .text, .data, .bss, ...}

yet if that storage needs to be saved to DRAM on any
exception, just in case the OS switches to a different
thread context, then I don't see how he can get his
claimed context switch times.

For interrupts, core starts fetching ISR thread state
before negotiating for an interrupt has finished. Most
of the time, the new state is arriving about when it is
known the interrupt will be "taken" by this core. Old
state is pushed out as new state arrives, then proceeds
to where is lives long term.