Re: is Vax addressing sane today

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Sun, 06 Oct 2024 08:40:55 GMT, Anton Ertl wrote:
>

Number of operand types never has been a criterion in any of the RISC
definitions I have seen, nor the number of instructions (although some
people like to go by that).

>
It’s in the name: "Reduced Instruction Set Computer".

Not at all.  What you think of is a "fewer instructions computer", but
it's called a "reduced-instruction set computer".  It becomes more
obvious if you look at the opposite: "Complex-instruction set
computer", not "more-instructions computer".

I always thought it should have been "IRSC": "Increased Register Set
Computer". The most obvious characteristic, the one that tends to hit you
first, is having lots of registers.

Having 32 GPRs does not make AMD64 with APX a RISC, and VAX (a CISC)
has the same number of registers as the first 801 and the ARM A32/T32
(RISCs).

However, in John Mashey's criteria the number of registers plays a
role; he requires >4 bits for the GPR specifier, and >3 bits for the
FPR specifier.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>