Re: 80286 protected mode

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Sujet : Re: 80286 protected mode
De : already5chosen (at) *nospam* yahoo.com (Michael S)
Groupes : comp.arch
Date : 07. Oct 2024, 15:45:19
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <20241007174519.00001d47@yahoo.com>
References : 1 2 3 4 5
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On Mon, 7 Oct 2024 15:17:36 +0200
Terje Mathisen <terje.mathisen@tmsw.no> wrote:

Lars Poulsen wrote:
On 2024-10-07, Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
 
Here's another speculation: The 286 protected mode was what they
already had in mind when they built the 8086, but there were not
enough transistors to do it in the 8086, so they did real mode,
and in the 80286 they finally got around to it.  And the idea was
(like AFAIK in the iAPX432) to have one segment per object and per
procedure, i.e., the large memory model.  The smaller memory
models were possible, but not really intended.  The Huge memory
model was completely alien to protected mode, as was direct
hardware access, as was common on the IBM PC.  And computing with
segment register contents was also not intended.
>
If programmers had used the 8086 in the intended way, porting to
protected mode would have been easy, but the programmers used it in
other ways, and the protected mode flopped.
>
Would it have been differently if the 8086/8088 had already had
protected mode?  I think that having one segment per object would
have been too inefficient, and also that 8192 segments is not
enough for that kind of usage, given 640KB of RAM (not to mention
the 16MB that the 286 supported); and with 640KB having the
segments limited to 64KB is too restrictive for a number of
applications. 
 
I completely agree. Back when the 8086 was designed, 640K seemed
like a lot. They never expected it to grow beyond the minframes of
their time. 
 
640K was an artifact of the frame buffer placement selected by the
original IBM PC, it could just as well have been 900+ K.
 
Afair the PC also mishandled interrupt handling?
 
Terje
 

Yes it did.
IIRC, Intel recommended interrupt slots 0 to 31 to be reserved for
hardware interrupts, but IBM ignored their recommendation and put
various BIOS at slots 16 to 31.


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3 Oct 24    ii `* Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress)219David Brown
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4 Oct 24    ii   +* Re: Byte ordering (was: Whether something is RISC or not)215Lawrence D'Oliveiro
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