Re: is Vax addressing sane today

On Sun, 6 Oct 2024 1:03:00 +0000, Lawrence D'Oliveiro wrote:

On Fri, 04 Oct 2024 07:05:34 GMT, Anton Ertl wrote:
>

CISC and RISC are about the instruction set, not about
the implementation.  And even if you look at the implementation, it's
not true: The P6 has microinstructions that are ~100 bits long, whereas
RISCs have 32-bit and 16-bit instructions. The K7 has load-store
microinstructions; RISCs don't have that.

>
Intel I think tried to spread this idea of a “RISC core” somewhere
inside
the labyrinthine complexity of its Pentium-and-later chips, in the hope
that some of the aura attached to the term “RISC” would rub off on its
products.
>
And quite a few people fell for it.
>

... ARM A64 and RISC-V are clearly RISCs.

>
ARM and some other RISC architectures (e.g. POWER) do somewhat stretch
the
term though, don’t they, when they add that combinatorial explosion of
operand types in their short-vector instructions.

600-1200 instructions in SIMD

RISC-V has consciously avoided this, by going back to the older long-
vector idea, like Seymour Cray used in his machines.

ONLY 100-300 instructions for long vector.
Compare this to 2 instructions in My 66000 that provide access
to both SIMD and long vectors.
In My Humble Opinion, ISAs with SIMD or Long Vectors do not qualify
as RISC.