Re: Interrupts in OoO

On Mon, 7 Oct 2024 19:59:59 +0000, Scott Lurndal wrote:

Brett <ggtgp@yahoo.com> writes:

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:

The CPU can give ring 0 priority, it is OoOe after all.

>
I assume you're referring to the Intel 64-bit x86_64 family,
as other processor families don't have a 'ring 0' per se.
>
The AArch64 architecture provides the ability to configure
the two processor interrupt signals to be delivered
independently at any one of three privilege (exception)
levels - kernel, hypervisor or secure monitor.

My 66000 provides the ability to configure any number of
interrupts (2^32) through any number of interrupt tables
(2^54) to any number of cores (2^16) at any of the 4
privilege levels and any of the 64 priority levels;
AND it requires no SW PIC updates on world-switches,
and control arrives in an already re-entrant state.

Usually configured to route FIQ (Fast interrupt) to
the most secure privilege level, and IRQ (interrupt)
to the next most privileged level (hypervisor or
bare metal OS).

Any interrupt in any table can be programmed to stimulate
any of the 4 (not just 3) privilege levels. User code
can be configured to take its own page faults without
an excursion through OS (except when called on by user
SVC).