Sujet : Re: 80286 protected mode
De : david.brown (at) *nospam* hesbynett.no (David Brown)
Groupes : comp.archDate : 13. Oct 2024, 12:58:14
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vegckn$ltgv$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
User-Agent : Mozilla Thunderbird
On 12/10/2024 20:33, Brett wrote:
David Brown <david.brown@hesbynett.no> wrote:
On 12/10/2024 01:32, MitchAlsup1 wrote:
On Fri, 11 Oct 2024 22:02:32 +0000, David Brown wrote:
>
On 11/10/2024 20:55, MitchAlsup1 wrote:
On Fri, 11 Oct 2024 12:10:13 +0000, David Brown wrote:
>
>
Do you think you can just write this :
>
void * memmove(void * s1, const void * s2, size_t n)
{
return memmove(s1, s2, n);
}
>
in your library's source?
>
.global memmove
memmove:
MM R2,R1,R3
RET
>
sure !
>
You are either totally clueless, or you are trolling. And I know you
are not clueless.
>
This discussion has become pointless.
>
The point is that there are a few things that may be hard to do
with {decode, pipeline, calculations, specifications...}; but
because they are so universally needed; these, too, should
"get into ISA".
>
One good reason to put them in ISA is to preserve the programmers
efforts over decades, so they don't have to re-write libc every-
time a new set of instructions come out.
>
Moving an arbitrary amount of memory from point a to point b
happens to fall into that universal need. Setting an arbitrary
amount of memory to a value also falls into that universal
need.
>
Again, I have to ask - do you bother to read the posts you reply to?
Are you interested in replying, and engaging in the discussion? Or are
you just looking for a chance to promote your own architecture, no
matter how tenuous the connection might be to other posts?
>
Again, let me say that I agree with what you are saying - I agree that
an ISA should have instructions that are efficient for what people
actually want to do. I agree that it is a good thing to have
instructions that let performance scale with advances in hardware
ideally without needing changes in compiled binaries, and at least
without needing changes in source code.
>
I believe there is an interesting discussion to be had here, and I would
enjoy hearing about comparisons of different ways things functions like
memcpy() and memset() can be implemented in different architectures and
optimised for different sizes, or how scalable vector instructions can
work in comparison to fixed-size SIMD instructions.
>
But at the moment, this potential is lost because you are posting total
shite about implementing memmove() in standard C. It is disappointing
that someone with your extensive knowledge and experience cannot see
this. I am finding it all very frustrating.
There are only two decisions to make in memcpy, are the copies less than
copy sized aligned, and do the pointers overlap in copy size.
Are you confused about memcpy() and memmove()? If so, let's clear that one up from the start. For memcpy(), there are no overlap issues - the person using it promises that the source and destination areas do not overlap, and no one cares what might happen if they do. For memmove(), the areas /may/ overlap, and the copy is done as though the source were copied first to a temporary area, and then from the temporary area to the destination.
For memcpy(), there can be several issues to consider for efficient implementations that can be skipped for a simple loop copying byte for byte. An efficient implementation will probably want to copy with larger sizes, such as using 32-bit, 64-bit, or bigger registers. For some targets, that is only possible for aligned data (and for some, unaligned accesses may be allowed but emulated by traps, making them massively slower than byte-by-byte accesses). The best choice of size will be implementation and target dependent, as will methods of determining alignment (if that is relevant). I'm guessing that by your somewhat muddled phrase "are the copies less than copy sized aligned", you meant something on those lines.
For memmove(), you generally also need to decide if your copy loop should run upwards or downwards, and that must be done in an implementation-dependent manner. It is conceivable that for a target with more complex memory setups - perhaps allowing the same memory to be accessible in different ways via different segments - that this is not enough.
For hardware this simplifies down to perhaps two types of copies, easy and
hard.
For most targets, yes.
If you make hard fast, and you will, then two versions is all you need, not
the dozens of choices with 1k of code you need in C.
That makes little sense. What "1k of code" do you need in C? Implementations of memcpy() and memmove() are implementation and target-specific, not general portable standard C. There is no single C implementation of these functions.
It is an obvious truism that if you have hardware instructions that can implement an efficient memcpy() and/or memmove() on a target, then the implementation-specific implementations of these functions on that target will be small, simple and efficient.
Often you know which of the two you want at compile time from the pointer
type.
In short your complaints are wrong headed in not understanding what
hardware memcpy can do.
What complaints? I haven't made any complains about implementing these functions.
Date | Sujet | # | | Auteur |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 237 | | Lawrence D'Oliveiro |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 236 | | David Brown |
16 Apr 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | MitchAlsup1 |
26 May 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | MitchAlsup1 |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 233 | | MitchAlsup1 |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 232 | | Thomas Koenig |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 225 | | MitchAlsup1 |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 223 | | Brett |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 222 | | Lawrence D'Oliveiro |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Brett |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Anton Ertl |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 219 | | David Brown |
3 Oct 24 | Byte ordering (was: Whether something is RISC or not) | 218 | | Anton Ertl |
3 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 1 | | David Brown |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 215 | | Lawrence D'Oliveiro |
4 Oct 24 | Re: Byte ordering | 1 | | Lynn Wheeler |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 211 | | David Brown |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 210 | | Anton Ertl |
4 Oct 24 | Re: Byte ordering | 5 | | BGB |
5 Oct 24 | Re: Byte ordering | 4 | | MitchAlsup1 |
5 Oct 24 | Re: Byte ordering | 2 | | BGB |
5 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 13 | | Lawrence D'Oliveiro |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 12 | | Brett |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 11 | | Anton Ertl |
5 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 10 | | Michael S |
6 Oct 24 | Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 8 | | Brett |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 7 | | Lawrence D'Oliveiro |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 6 | | Brett |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 5 | | Michael S |
7 Oct 24 | Re: Byte ordering | 2 | | Stefan Monnier |
7 Oct 24 | Re: Byte ordering | 1 | | Michael S |
7 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 | Re: Byte ordering | 191 | | David Brown |
6 Oct 24 | Re: Byte ordering | 190 | | Anton Ertl |
6 Oct 24 | Re: Byte ordering | 189 | | John Dallman |
7 Oct 24 | Re: Byte ordering | 20 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: Byte ordering | 19 | | John Dallman |
9 Oct 24 | VMS/NT memory management (was: Byte ordering) | 1 | | Stefan Monnier |
15 Oct 24 | Re: Byte ordering | 2 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 1 | | MitchAlsup1 |
15 Oct 24 | Re: Byte ordering | 15 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 3 | | Michael S |
15 Oct 24 | Re: Byte ordering | 1 | | John Dallman |
18 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
15 Oct 24 | Re: Byte ordering | 9 | | John Dallman |
16 Oct 24 | Re: Byte ordering | 7 | | George Neuner |
16 Oct 24 | Re: Byte ordering | 6 | | Terje Mathisen |
16 Oct 24 | Re: Byte ordering | 5 | | David Brown |
17 Oct 24 | Re: Byte ordering | 2 | | George Neuner |
17 Oct 24 | Re: Byte ordering | 1 | | David Brown |
17 Oct 24 | Re: clouds, not Byte ordering | 2 | | John Levine |
17 Oct 24 | Re: clouds, not Byte ordering | 1 | | David Brown |
18 Oct 24 | Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
16 Oct 24 | Re: Byte ordering | 2 | | Paul A. Clayton |
18 Oct 24 | Re: Microkernels & Capabilities (was Re: Byte ordering) | 1 | | Lawrence D'Oliveiro |
7 Oct 24 | 80286 protected mode | 168 | | Anton Ertl |
7 Oct 24 | Re: 80286 protected mode | 5 | | Lars Poulsen |
7 Oct 24 | Re: 80286 protected mode | 4 | | Terje Mathisen |
7 Oct 24 | Re: 80286 protected mode | 1 | | Michael S |
7 Oct 24 | Re: 80286 protected mode | 2 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 1 | | Terje Mathisen |
7 Oct 24 | Re: 80286 protected mode | 3 | | Brett |
7 Oct 24 | Re: 80286 protected mode | 2 | | Michael S |
7 Oct 24 | Re: 80286 protected mode | 1 | | Brett |
7 Oct 24 | Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 152 | | MitchAlsup1 |
8 Oct 24 | Re: 80286 protected mode | 4 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 3 | | MitchAlsup1 |
9 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
15 Oct 24 | Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 | Re: 80286 protected mode | 147 | | Anton Ertl |
8 Oct 24 | Re: 80286 protected mode | 1 | | Robert Finch |
9 Oct 24 | Re: 80286 protected mode | 145 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 79 | | MitchAlsup1 |
9 Oct 24 | Re: 80286 protected mode | 78 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 77 | | Stephen Fuld |
10 Oct 24 | Re: 80286 protected mode | 2 | | MitchAlsup1 |
10 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
10 Oct 24 | Re: 80286 protected mode | 1 | | David Brown |
11 Oct 24 | Re: 80286 protected mode | 73 | | Tim Rentsch |
15 Oct 24 | Re: 80286 protected mode | 72 | | Stefan Monnier |
15 Oct 24 | Re: 80286 protected mode | 30 | | MitchAlsup1 |
16 Oct 24 | Re: 80286 protected mode | 25 | | MitchAlsup1 |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 13 | | John Levine |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 7 | | MitchAlsup1 |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 6 | | John Levine |
17 Oct 24 | Re: C and turtles, 80286 protected mode | 5 | | Thomas Koenig |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 4 | | Lawrence D'Oliveiro |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 3 | | George Neuner |
22 Oct 24 | Re: C and turtles, 80286 protected mode | 2 | | Tim Rentsch |
22 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | George Neuner |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | David Brown |
16 Oct 24 | Re: C and turtles, 80286 protected mode | 4 | | Paul A. Clayton |
17 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | David Brown |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 2 | | Lawrence D'Oliveiro |
20 Oct 24 | Re: C and turtles, 80286 protected mode | 1 | | Paul A. Clayton |
16 Oct 24 | Re: 80286 protected mode | 7 | | Thomas Koenig |
17 Oct 24 | Re: 80286 protected mode | 3 | | George Neuner |
17 Oct 24 | Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 | Re: 80286 protected mode | 3 | | David Brown |
17 Oct 24 | Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 | Re: 80286 protected mode | 41 | | David Brown |
9 Oct 24 | Re: 80286 protected mode | 51 | | Thomas Koenig |
13 Oct 24 | Re: 80286 protected mode | 14 | | Anton Ertl |
8 Oct 24 | Re: 80286 protected mode | 6 | | John Levine |
6 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Michael S |
4 Oct 24 | Re: Byte ordering (was: Whether something is RISC or not) | 1 | | John Dallman |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Thomas Koenig |
2 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 5 | | David Schultz |
3 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Lawrence D'Oliveiro |