Sujet : Re: MM instruction and the pipeline
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.archDate : 17. Oct 2024, 22:49:19
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <4a034257ae8658ecd8fb35777ae30380@www.novabbs.org>
References : 1 2 3 4
User-Agent : Rocksolid Light
On Thu, 17 Oct 2024 17:16:24 +0000, EricP wrote:
Stephen Fuld wrote:
On 10/16/2024 12:26 PM, MitchAlsup1 wrote:
>
MM is a (long) series of byte LD and ST to virtual addresses.
The ordering rules for MM relative to scalar LD and ST before and after
it should be no different, other than the exact order of individual MM
bytes moved is not defined other than it is overlap safe.
>
But the same bypassing and forwarding rules apply.
E.g. Under TSO, MM being a sequence of stores cannot start until it is
at the end of the Load Store Queue and ready to retire. So all older LD
and
ST must have retired and we only need consider interactions of MM with
younger LD and ST.
My 66000 is NOT TSO it is causal unless special areas are being
accessed.
But, yes, MM must operate as if it is ordered with other memory
reference
instructions.
If an implementation allows a younger LD [x] to bypass an older
MM &dst, &src, then LSQ must retain the LD [x] someplace so it can
check if at some later time, perhaps far later, that a MM store to the
physical address of &dst overlaps the physical address of [x].
If it does overlap then LSQ must trigger a replay of the younger LD [x]
so it picks up the new value from dst buffer.
No essential disagreement.
A younger store ST to any address cannot be seen to bypass an older MM
store to any address, though it could prefetch.
Once again it is not TSO.