Re: Misc: BGBCC targeting RV64G, initial results...

On Mon, 21 Oct 2024 20:13:20 +0000, BGB wrote:

On 10/17/2024 9:28 PM, MitchAlsup1 wrote:

Granted, I guess it could be decoded as if it were a normal 3RI op or
similar, but then split up the immediate into multiple parts in EX1.

>
Why would you want do make it 3×11-bit displacements when you can
make it 3×16-bit displacements.
>
     +------+-----+-----+----------------+
     | Bc   |  3W |  Rt |   .lb_lo       |
     +------+-----+-----+----------------+
     |   .lb_zero       |  .lb_hi        |
     +------------------+----------------+

>
Neither BJX2 nor RISC-V have the encoding space to pull this off...
   Even in a clean-slate ISA, it would be a big ask.

If you remove compressed instructions from RISC-V, you have enough
room left over to put the entire My 66000 ISA. ... ... ...