Re: Privilege Levels Below User

On Sun, 9 Jun 2024 2:23:35 +0000, Lawrence D'Oliveiro wrote:

On Sat, 8 Jun 2024 17:37:46 +0000, MitchAlsup1 wrote:
>

VAX was before common era Hypervisors, do you think VAX could have
supported secure mode and hypervisor with their 4 levels ??

>
“Virtualization” was bandied about in the 1980s more as an idle,
theoretical concept rather than a practical one.
>
The question was: was the instruction set defined so that code that was
designed to run in a privileged mode be run unprivileged, so that any
attempt to do privileged things would be trapped and emulated by the
real privileged code? And there was nothing it could do to discover
it wasn’t running in privileged mode?

My 66000 ISA has this property, and it is used when hypervisors host
hypervisors.
On the other hand, there is only 1 privileged instruction which
provides access to 4 separate control register spaces based on
current Core-Stack level.

(Obviously performance was not the issue here, but correctness was.)
>
For example, the VAX had a MOVPSL instruction that allowed read-only
access to the entire processor status register. Through this,
nonprivileged user-mode code could discover it was running in user mode,
which would blow the illusion.

While illustrative, we have entered the realm where processor state
is closer to a cache line in size than a register in size. And the
processor (core) stack of software layers is closer to 4 cache lines
in size.

The Motorola 680x0 family was I think properly virtualizable in this
sense. Or maybe the 68020 and 68030 were, but the 68040 was. I think the
Motorola engineers working on the ’040 asked if any customers were
interested in preserving the self-virtualization feature, and nobody
seemed to care.

During 020 development and testing, there was a mode whereby each
instruction executed raised every possible exception--this only found
99% of the virtualization problems.