Re: Q+ Fibonacci

Reached a milestone: got the Q+ CPU to execute Fibonacci in SIM. The CPU is working in serial mode.
Backout and restore handling for branches is disabled. Instead, instructions following the branch that should not be executed are turned into copy-targets, that copy the target register to the new target register. Since the ROB is only 16 entries this can be done in about the same length of time as a backout and restore.
The target register is already being read for predication purposes.
Converting instructions to copy-targets means that checkpoints are not needed, so the core size can be reduced. It may cost a little bit in performance. 3 or 4 instructions can be skipped over per clock with copy-targets, compared to single instruction backout per clock.