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EricP <ThatWouldBeTelling@thevillage.com> writes:Ohhhhhh... That's nice! So, we can use both flavors wrt optimistic and pessimistic? Fwiw, I still did not get a chance to read up on the docs you so kindly linked me to.Chris M. Thomasson wrote:Aarch64 also has CASP, a 128-bit atomic compare and swapOn 11/8/2024 2:56 PM, Chris M. Thomasson wrote:>>>
Perhaps sometime tonight. Is seems like optimistic LL/SC instead of
pessimistic CAS RMW type of logic?
LL/SC vs cmpxchg8b?
Arm A64 has LDXP Load Exclusive Pair of registers and
STXP Store Exclusive Pair of registers looks like it can be
equivalent to cmpxchg16b (aka double-wide compare and swap).
instruction.
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