Re: Arm ldaxr / stxr loop question

On Mon, 11 Nov 2024 13:59:22 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Sun, 10 Nov 2024 21:00:23 +0000, EricP wrote:
 

Scott Lurndal wrote: 

EricP <ThatWouldBeTelling@thevillage.com> writes: 

Chris M. Thomasson wrote: 

On 11/8/2024 2:56 PM, Chris M. Thomasson wrote: 

Perhaps sometime tonight. Is seems like optimistic LL/SC
instead of pessimistic CAS RMW type of logic? 

LL/SC vs cmpxchg8b? 

Arm A64 has LDXP Load Exclusive Pair of registers and
STXP Store Exclusive Pair of registers looks like it can be
equivalent to cmpxchg16b (aka double-wide compare and swap). 

>
Aarch64 also has CASP, a 128-bit atomic compare and swap
instruction. 

>
Thanks, I missed that.
>
Any idea what is the advantage for them having all these various
LDxxx and STxxx instructions that only seem to combine a LD or ST
with a fence instruction? 

>
The advantage is consuming OpCode space at breathtaking speed.
Oh wait...
 

Why have
LDAPR Load-Acquire RCpc Register
LDAR Load-Acquire Register
LDLAR LoadLOAcquire Register 

>
Because the memory model was not build with the notion of memory
order and that not all ATOMIC events start or end with a
recognizable inst- ruction. Having ATOMICs announce their beginning
and ending eliminates the need for fencing; even if you keep a
<relatively> relaxed memory order model. 

 
There are fully atomic instructions,  the load/store exclusives are
generally there for backward compatability with armv7; the full set
of atomics (SWP, CAS, Atomic Arithmetic Ops, etc) arrived with
ARMv8.1.
 

Also for compatibility with Cortex-A53 which is still a significant
part of installed base.