Re: Arm ldaxr / stxr loop question

On 11/11/24 08:59, Scott Lurndal wrote:

 There are fully atomic instructions,  the load/store exclusives are
generally there for backward compatability with armv7; the full set
of atomics (SWP, CAS, Atomic Arithmetic Ops, etc) arrived with
ARMv8.1.
 

They added the atomics for scalability allegedly.  ARM never
stated what the actual issue was.  I suspect they couldn't
guarantee a memory lock size small enough to eliminate
destructive interference.  Like cache line size instead
of word size.
Joe Seigh