Re: Arm ldaxr / stxr loop question

On 11/11/2024 9:11 AM, Scott Lurndal wrote:

EricP <ThatWouldBeTelling@thevillage.com> writes:

Scott Lurndal wrote:

EricP <ThatWouldBeTelling@thevillage.com> writes:

Scott Lurndal wrote:

EricP <ThatWouldBeTelling@thevillage.com> writes:

Chris M. Thomasson wrote:

On 11/8/2024 2:56 PM, Chris M. Thomasson wrote:

Perhaps sometime tonight. Is seems like optimistic LL/SC instead of
pessimistic CAS RMW type of logic?

LL/SC vs cmpxchg8b?

Arm A64 has LDXP Load Exclusive Pair of registers and
STXP Store Exclusive Pair of registers looks like it can be
equivalent to cmpxchg16b (aka double-wide compare and swap).

Aarch64 also has CASP, a 128-bit atomic compare and swap
instruction.

Thanks, I missed that.
>
Any idea what is the advantage for them having all these various
LDxxx and STxxx instructions that only seem to combine a LD or ST
with a fence instruction? Why have
LDAPR Load-Acquire RCpc Register
LDAR Load-Acquire Register
LDLAR LoadLOAcquire Register
>
plus all the variations for byte, half, word, and pair,
instead of just the standard LDx and a general data fence instruction?
>
The execution time of each is the same, and the main cost is the fence
synchronizing the Load Store Queue with the cache, flushing the cache
comms queue and waiting for all outstanding cache ops to finish.
>

>
  "Limited ordering regions allow large systems to perform
   special Load-Acquire and Store-Release instructions that
   provide order between the memory accesses to a region of
   the PA map as observed by a limited set of observers."

>
Ok, so that explains LoadLOAcquire, StoreLORelease as they are
functionally different: it needs to associate the fence with specific
load and store addresses so it can determine a physical LORegion,
if any, and thereby limit the scope of the fence actions to that LOR.
>
But that doesn't explain Load-Acquire, Load-AcquirePC, and Store-Release.
Why attach a specific kind of fence action to the general LD or ST?
They do the same thing in the atomic instructions, eg:

 Note that the atomics were added in V8.1, and were optional at that
time.
  From the ARMv8 ARM:
      Arm provides a set of instructions with Acquire semantics for
     loads, and Release semantics for stores. These instructions
     support the Release Consistency sequentially consistent (RCsc) model.
     In addition, FEAT_LRCPC provides Load-AcquirePC instructions. The
     combination of Load-AcquirePC and Store-Release can be use to
     support the weaker Release Consistency processor consistent (RCpc) model.

It sure seems like the "weaker" release is similar to unlocking a spinlock with a store in x86, MOV because it already has implied release membar semantics aka (#LoadStore | #StoreStore).