Re: Arm ldaxr / stxr loop question

On 11/11/2024 1:53 PM, Chris M. Thomasson wrote:

On 11/11/2024 6:56 AM, jseigh wrote:

On 11/11/24 08:59, Scott Lurndal wrote:
>

>
There are fully atomic instructions,  the load/store exclusives are
generally there for backward compatability with armv7; the full set
of atomics (SWP, CAS, Atomic Arithmetic Ops, etc) arrived with
ARMv8.1.
>

>
They added the atomics for scalability allegedly.  ARM never
stated what the actual issue was.  I suspect they couldn't
guarantee a memory lock size small enough to eliminate
destructive interference.  Like cache line size instead
of word size.

 For some reason it reminds me of the size of a reservation granule wrt LL/SC.

For some reason I remember way back wrt having to pad and align things on reservation granule's back on PPC. Iirc, it was the "anchor" structure. The nodes were aligned and padded up to l2 cache lines. This was 20+ years ago! damn it. Time goes by. Uggg. ;^o