Re: Arm ldaxr / stxr loop question

On 11/12/2024 4:32 PM, Chris M. Thomasson wrote:

On 11/12/2024 3:02 PM, aph@littlepinkcloud.invalid wrote:

Chris M. Thomasson <chris.m.thomasson.1@gmail.com> wrote:

On 11/12/2024 4:14 AM, aph@littlepinkcloud.invalid wrote:

>
One other thing to be aware of is that the StoreLoad barrier needed
for sequential consistency is logically part of an LDAR, not part of a
STLR. This is an optimization, because the purpose of a StoreLoad in
that situation is to prevent you from seeing your own stores to a
location before everyone else sees them.

>
Fwiw, even x86/x64 needs StoreLoad when an algorithm depends on a
store followed by a load to another location to hold. LoadStore is
not strong enough. The SMR algorithm needs that. Iirc, Peterson's
algorithms needs it as well.

>
That's right, but my point about LDAR on AArch64 is that you can get
sequential consistency without needing a StoreLoad.

 Ahhh. So, well, it makes me think of the implied StoreLoad in x86/x64 LOCK'ed RMW's...? Does this make any sense to you? Or, am I wandering around in a damn field somewhere! ;^o
 I am so used to SPARC style in RMO mode. The LoadStore should be _after_ any "naked", but atomic logic that acquires and releases a spinlock...

I need to clarify here. Shit. The LoadStore LoadLoad should be after the atomic logic that acquires the spinlock. It should be before the release LoadStore StoreStore that should occur before the atomic logic that releases the spinlock. Humm... How much more complicated can I make it? Sorry.
__________
naked_atomic_lock()
    membar #LoadStore | #LoadLoad
       // locked region
    membar #LoadStore | #StoreStore
naked_atomic_unlock();
__________
Damn it. Sorry everybody!
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