Re: Brilliance

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Sujet : Re: Brilliance
De : cr88192 (at) *nospam* gmail.com (BGB)
Groupes : comp.arch
Date : 13. Nov 2024, 20:40:32
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vh2vbt$2c1kn$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
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On 11/13/2024 4:20 AM, Anton Ertl wrote:
Terje Mathisen <terje.mathisen@tmsw.no> writes:
To me brilliant is something that still isn't obvious after larning
about it.
 Why do you think it's less brilliant to recognize something obvious
that everybody else has overlooked?
 
Yeah.
This is my feelings about some of the deficiencies of standard RISC-V.
The stuff I want added, and have added as experiments, is not exactly non-obvious. Saw at least one person doubting that it would make much difference (namely in the use of "make the immediate bigger" prefixes).
But, experimentally, it does make enough of a difference that it should be worth considering, at least for performance-oriented use-cases (likely, not really needed for microcontrollers, where the priority is more "cheap CPU" rather than "fast CPU").
But, as I see it, if you can make binaries 40% smaller, and 35% faster, this is something that should be worth considering.
As opposed to the C extension which IME seems to only give around a 25-30% size reduction, and (with a CPU design that only does superscalar on properly aligned 32-bit instructions) actually makes performance slightly worse.
Granted, having both jumbo prefixes and the 'C' extension being likely a best case for code density (though, BGBCC doesn't yet support the 'C' extension, so I can't test this).
I am half tempted to move the RV jumbo prefixes from
   ...-100-kkkkk-00-11011 (ALUIW block)
To:
   ...-100-kkkkk-00-00111 (JALR block)
For "technical reasons" (well, would also clean up the encoding conflict with an older/dropped "ADDIWU" instruction). TBD if worth the break in compatibility though (if I did so, might consider also claiming 1xx for jumbo prefixes, say, to give an extra bit so that "JIMM+JIMM+LUI" could have enough bits to encode F0..F31 as well, but there are other possibilities for how to encode this).
Most of these features have historical precedent as well, so should in theory be "safe" (similar sorts of prefixes existed in Transputer and Java VM).
Granted, not found examples thus far in 1980s or 1990s RISC architectures (these sorts of prefixes didn't really seem to start appearing in RISC's until the early 2000s). Annoyingly, most precedent for the use of prefixes and prefix instructions seems to be in terms of CISC architectures.
The closest direct equivalent of the Jumbo_Imm prefix I am aware of didn't appear until MicroBlaze, which is cutting it a little close (and have yet to verify if it existed in the original version of MicroBlaze). In any case, will probably be more safe in a few years (as MiceoBlaze moves further outside of the 20 year window).
Register-Indexed Load/Store and similar were fairly widespread (80386, ARM32, and others), so should be safe.
Can note that also, in BJX2, the general ideas behind WEX encoding also had precedent (was in use in 1990s DSP architectures and similar), ...
Sometimes, there is an elegance in finding things sufficiently obvious that it is more a question why it is not more widespread.
Or, avoiding things that require a non-trivial leap in logic, or pose difficulty in verifying the logic chains.
Though, arguably, in terms of precedent, something like RISC-V is arguably fairly safe:
Its core ISA lacks anything that didn't already have precedent by the early 1980s.
But, as I see it, pretty much anything that has precedent earlier than ~2004 should be safe (which, as I see it, should include things like jumbo prefixes, etc).
...
There are, granted, potential gotchas, like the years of hassle that S3TC and depth-fail shadows and similar caused.
Where, S3TC should have been invalid, as it wasn't substantially different from what was already in common use in the 1980s.
Seemingly, main arguable "novel" feature it had was defining the interpolated colors as 1/3 + 2/3 rather than 1-bit (A or B), or 3/8 + 5/8 (as in some earlier Apple image formats).
There was the "S2TC" workaround (just disallow interpolation entirely); theoretically though, someone could have just used DXT1/DXT5 mostly as is, but then redefined the interpolation as 3/8 + 5/8 as "close enough"...
Similarly the depth-fail issue was also annoying. There was still depth-pass though, but this had some annoying edge cases that required workarounds (the shadows would break if the camera was inside a shadow volume, requiring a workaround).
Depth-fail shadows should also be safe now.
...
Well, and people can freely use FAT32, or (in theory) NTFS. Though, the design of NTFS itself is a bigger impediment to using it; though with some limited (newer features may still not be safe).
A person should also be able to do their own off-brand implementations of x86-64 (*) and 32-bit ARM and Thumb/Thumb2.
*: The original form of x86-64 should be safe, would mostly need to omit newer forms of SSE, and AVX, to be safe.
...
May not be obvious, but admittedly, I am more someone that tries to avoid "novelty" (often things like cost/benefit concerns and historical precedent are given more weight).

- anton

Date Sujet#  Auteur
28 Oct 24 * Arm ldaxr / stxr loop question135jseigh
31 Oct 24 +- Re: Arm ldaxr / stxr loop question1MitchAlsup1
31 Oct 24 +- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
1 Nov 24 +* Re: Arm ldaxr / stxr loop question123aph
2 Nov 24 i`* Re: Arm ldaxr / stxr loop question122Chris M. Thomasson
8 Nov 24 i `* Re: Arm ldaxr / stxr loop question121Chris M. Thomasson
9 Nov 24 i  `* Re: Arm ldaxr / stxr loop question120Chris M. Thomasson
9 Nov 24 i   +* Re: Arm ldaxr / stxr loop question117Chris M. Thomasson
9 Nov 24 i   i+- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
11 Nov 24 i   i+* Re: Arm ldaxr / stxr loop question5MitchAlsup1
11 Nov 24 i   ii+- Re: Arm ldaxr / stxr loop question1Michael S
11 Nov 24 i   ii`* Re: Arm ldaxr / stxr loop question3jseigh
11 Nov 24 i   ii `* Re: Arm ldaxr / stxr loop question2Chris M. Thomasson
13 Nov 24 i   ii  `- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
11 Nov 24 i   i+- Re: Arm ldaxr / stxr loop question1Michael S
12 Nov 24 i   i+- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
12 Nov 24 i   i+* Re: Arm ldaxr / stxr loop question22aph
13 Nov 24 i   ii+* Re: Arm ldaxr / stxr loop question18Chris M. Thomasson
13 Nov 24 i   iii`* Re: Arm ldaxr / stxr loop question17aph
13 Nov 24 i   iii +* Re: Arm ldaxr / stxr loop question3jseigh
13 Nov 24 i   iii i`* Re: Arm ldaxr / stxr loop question2aph
13 Nov 24 i   iii i `- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
13 Nov 24 i   iii +- Re: Arm ldaxr / stxr loop question1MitchAlsup1
13 Nov 24 i   iii +* Re: Arm ldaxr / stxr loop question2Chris M. Thomasson
13 Nov 24 i   iii i`- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
13 Nov 24 i   iii +* Re: Arm ldaxr / stxr loop question2Chris M. Thomasson
13 Nov 24 i   iii i`- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
13 Nov 24 i   iii `* Re: Arm ldaxr / stxr loop question8Terje Mathisen
13 Nov 24 i   iii  +* Brilliance (was: Arm ldaxr / stxr loop question)4Anton Ertl
13 Nov 24 i   iii  i+- Re: Brilliance1BGB
14 Nov 24 i   iii  i`* Re: Brilliance2Terje Mathisen
17 Nov 24 i   iii  i `- Re: Brilliance1Thomas Koenig
13 Nov 24 i   iii  `* Re: Arm ldaxr / stxr loop question3aph
14 Nov 24 i   iii   `* Re: Arm ldaxr / stxr loop question2Terje Mathisen
15 Nov 24 i   iii    `- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
13 Nov 24 i   ii`* Re: Arm ldaxr / stxr loop question3BGB
13 Nov 24 i   ii `* Re: Arm ldaxr / stxr loop question2Chris M. Thomasson
13 Nov 24 i   ii  `- Re: Arm ldaxr / stxr loop question1Robert Finch
14 Nov 24 i   i`* Re: Arm ldaxr / stxr loop question86Kent Dickey
14 Nov 24 i   i `* Re: Arm ldaxr / stxr loop question85aph
15 Nov 24 i   i  +* Re: Arm ldaxr / stxr loop question81Chris M. Thomasson
15 Nov 24 i   i  i`* Re: Arm ldaxr / stxr loop question80aph
15 Nov 24 i   i  i +- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson
15 Nov 24 i   i  i `* Memory ordering (was: Arm ldaxr / stxr loop question)78Anton Ertl
15 Nov 24 i   i  i  +* Re: Memory ordering44Chris M. Thomasson
15 Nov 24 i   i  i  i`* Re: Memory ordering43Michael S
15 Nov 24 i   i  i  i `* Re: Memory ordering42Chris M. Thomasson
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17 Nov 24 i   i  i  i    +* Re: Memory ordering33Anton Ertl
19 Nov 24 i   i  i  i    i`* Re: Memory ordering32Chris M. Thomasson
3 Dec 24 i   i  i  i    i `* Re: Memory ordering31Anton Ertl
3 Dec 24 i   i  i  i    i  `* Re: Memory ordering30jseigh
3 Dec 24 i   i  i  i    i   `* Re: Memory ordering29MitchAlsup1
4 Dec 24 i   i  i  i    i    +* Re: Memory ordering22Stefan Monnier
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18 Dec12:43 i   i  i  i    i    i  i   `* Re: Memory ordering2jseigh
19 Dec03:48 i   i  i  i    i    i  i    `- Re: Memory ordering1Chris M. Thomasson
19 Dec19:33 i   i  i  i    i    i  `* Re: Memory ordering8MitchAlsup1
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4 Dec 24 i   i  i  i    i    +- Re: Memory ordering1MitchAlsup1
5 Dec 24 i   i  i  i    i    `* Re: Memory ordering4Tim Rentsch
6 Dec 24 i   i  i  i    i     +* Re: Memory ordering2Terje Mathisen
6 Dec 24 i   i  i  i    i     i`- Re: Memory ordering1Tim Rentsch
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17 Nov 24 i   i  i  i    +* Re: Memory ordering2Chris M. Thomasson
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18 Nov 24 i   i  i  i    +- Re: Memory ordering1aph
21 Nov 24 i   i  i  i    +- Re: Memory ordering1Chris M. Thomasson
21 Nov 24 i   i  i  i    `- Re: Memory ordering1Chris M. Thomasson
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15 Nov 24 i   i  i  i`- Re: Memory ordering (was: Arm ldaxr / stxr loop question)1Anton Ertl
15 Nov 24 i   i  i  +* Re: Memory ordering28jseigh
15 Nov 24 i   i  i  i`* Re: Memory ordering27Anton Ertl
15 Nov 24 i   i  i  i +* Re: Memory ordering18Chris M. Thomasson
16 Nov 24 i   i  i  i i`* Re: Memory ordering17Anton Ertl
17 Nov 24 i   i  i  i i `* Re: Memory ordering16Chris M. Thomasson
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18 Nov 24 i   i  i  i i   `* Re: Memory ordering14Chris M. Thomasson
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19 Nov 24 i   i  i  i i     `* Re: Memory ordering12Chris M. Thomasson
19 Nov 24 i   i  i  i i      `* Re: Memory ordering11Chris M. Thomasson
26 Nov 24 i   i  i  i i       +* Re: Memory ordering4Chris M. Thomasson
3 Dec 24 i   i  i  i i       `* Re: Memory ordering6Anton Ertl
15 Nov 24 i   i  i  i +* Re: Memory ordering7BGB
17 Nov 24 i   i  i  i `- Re: Memory ordering1Tim Rentsch
16 Nov 24 i   i  i  +- Re: Memory ordering (was: Arm ldaxr / stxr loop question)1Anton Ertl
16 Nov 24 i   i  i  +- Re: Memory ordering (was: Arm ldaxr / stxr loop question)1Lawrence D'Oliveiro
18 Nov 24 i   i  i  `- Re: Memory ordering1aph
21 Nov 24 i   i  `* Re: Arm ldaxr / stxr loop question3Kent Dickey
9 Nov 24 i   `* Re: Arm ldaxr / stxr loop question2jseigh
8 Nov 24 +* Re: Arm ldaxr / stxr loop question8Lawrence D'Oliveiro
20 Dec10:11 `- Re: Arm ldaxr / stxr loop question1Chris M. Thomasson

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