Re: Memory ordering (was: Arm ldaxr / stxr loop question)

scott@slp53.sl.home (Scott Lurndal) writes:

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

Was it an actual behaviour of any Alpha for public sale, or was it
just the Alpha specification?

...

Perhaps one might ask Dr. Kessler?
>
https://acg.cis.upenn.edu/milom/cis501-Fall09/papers/Alpha21264.pdf

I don't think that anything in the 21264 core would result in the
Alpha-unique inconsistency; the only core mechanisms that I can think
of where that would be relevant is value prediction, and the 21264
does not do that.

Looking at the memory subsystems of bigger Alpha systems might be more
relevant.

There is a good reason to suspect that the Alpha architects imagined
hardware that actually did not appear: They did not specify hardware
byte and 16-bit memory accesses with the justification that a
first-level write-back cache would require ECC in DEC machines, and
ECC for bytes (or read-modify-write for keeping ECC on larger units)
is supposedly too expensive.  However, the Alphas without BWX
instructions (everything up to EV5, but EV56 and later acquired BWX)
never had a first-level write-back cache.

And the EV6 which has a first-level write-back cache, implements the
BWX instructions, so the reasoning against BWX obviously does not hold
water.  Reading on page 31 of the paper above, the 21264 (EV6) uses
read-modify-write for updating the ECC data.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>