Re: What do we call non-pipelined designs?

On Sun, 8 Dec 2024 22:10:15 +0000, Marcus wrote:

I usually (and simplistically) divide CPU designs (implementations) into
two main categories:
>
- Pipelined
- Non-pipelined
>
Of course, there is a sliding scale at play, but let's not get into that
debate.
>
My question is: What is the best name for non-pipelined designs?

If any portion of the design fetches the next instruction before the
last calculation of the previous instruction, then the design is
pipelined. CDC 6600 had a pipelined front end and serially reusable
calculation units. {{Also note under this definition 6800, 68000, and
8086 were (partially pipelined) architectures.

I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.

Given that one can take an off the shelf (rather cheap) FPGA and
implement a fully pipeline RISC ISA implementation::
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?

/Marcus