Sujet : Re: What do we call non-pipelined designs?
De : Keith.S.Thompson+u (at) *nospam* gmail.com (Keith Thompson)
Groupes : comp.archDate : 09. Dec 2024, 03:45:09
Autres entêtes
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Marcus <
m.delete@this.bitsnbites.eu> writes:
I usually (and simplistically) divide CPU designs (implementations) into
two main categories:
>
- Pipelined
- Non-pipelined
>
Of course, there is a sliding scale at play, but let's not get into that
debate.
>
My question is: What is the best name for non-pipelined designs?
I can't think of anything better or clearer than "non-pipelined designs".
I'm thinking about CPU:s that transition through several states (one
clock cycle after another) when executing a single instruction (e.g.
FETCH + DECODE + EXECUTE), and where instruction and data typically
share the same memory interface.
-- Keith Thompson (The_Other_Keith) Keith.S.Thompson+u@gmail.comvoid Void(void) { Void(); } /* The recursive call of the void */
What do we call non-pipelined designs?
Re: What do we call non-pipelined designs?
