Re: portable proxy collector test...

On 12/8/24 18:31, Chris M. Thomasson wrote:

On 12/6/2024 2:43 PM, jseigh wrote:

On 12/6/24 16:12, Chris M. Thomasson wrote:

On 12/6/2024 11:55 AM, Brett wrote:

Chris M. Thomasson <chris.m.thomasson.1@gmail.com> wrote:

I am wondering if anybody can try to compile and run this C++11 code of
mine for a portable word-based proxy collector, a sort of poor mans RCU,
on an ARM based system? I don't have access to one. I am interested in
the resulting output.

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https://godbolt.org
>

https://pastebin.com/raw/CYZ78gVj
(raw text link, no ads... :^)

[...]
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It seems that all of the atomics are LDREX/STREX wrt fetch_add/sub . Even with relaxed memory order. Are the LDREX/STREX similar to the LOCK prefix on an x86/64?
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https://godbolt.org/z/EPGYWve71
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It has loops for this in the ASM code. Adding a loop in there can change things from wait-free to lock-free. Humm...
>

Which compiler did you choose.  armv8?  Try ARM64.
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The newer arms have new atomics
cas and atomic fetch ops.
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LDREX/STREX is the older load store reserved.
On the newer stuff it's ldxr/stxr not ldrex/strex.

 Well, for a ARM64 gcc 14.2.0 a relaxed fetch_add I get __aarch64_ldadd8_acq_rel in the asm.
 https://godbolt.org/z/YzPdM8j33
 acq_rel barrier for a relaxed membar? Well, that makes me go grrrrrr!
 It has to be akin to the LOCK prefix over on x86. I want it relaxed damn it! ;^)

Apart of the memory ordering, if you are using atomic_fetch_add you
are going to get an interlocked instruction which is probably
overkill and has more overhead than you want.   Atomic ops
assume other cpus might be trying atomic rmw ops on other
cpus which is not the case for userspace rcu.  You want
an atomic relaxed load, and atomic relaxed store of the
incrmented value.  It will be faster.
Joe Seigh