Sujet : Re: What do we call non-pipelined designs?
De : david.schultz (at) *nospam* earthlink.net (David Schultz)
Groupes : comp.archDate : 09. Dec 2024, 18:20:55
Autres entêtes
Message-ID : <1d2dnfrKM4Bju8r6nZ2dnZfqn_adnZ2d@earthlink.com>
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User-Agent : Mozilla Thunderbird
On 12/8/24 9:43 PM, Lawrence D'Oliveiro wrote:
On Sun, 8 Dec 2024 23:05:40 +0000, MitchAlsup1 wrote:
Why, in this day and age, would anyone want to even consider doing
something less pipelined than that ?!?!?
Here’s one reason (tell me if I’m wrong): I remember some CPU designs used
CMOS and probably some other hardware magic I don’t understand to create
chips that could run at any speed down to 0Hz.
It required zero hardware magic. It was a design choice.
A dynamic latch required fewer transistors (area) but imposed a minimum clock speed to keep the stored charge from leaking away to uselessness. A static latch had no minimum speed but required more transistors.
In those early days with CPU transistor counts in the thousands, dynamic latches were a good and fairly common choice.
-- http://davesrocketworks.comDavid Schultz