Re: Strange asm generated by GCC...

jseigh <jseigh_es00@xemaps.com> wrote:

On 12/19/24 19:43, Chris M. Thomasson wrote:

Why in the world would GCC use an XCHG instruction for the following
code. The damn XCHG has an implied LOCK prefix! Yikes!
 

 
Speaking of strange code
 
#include <atomic>
 
bool test1(std::atomic<int> var, int addend)
{
    int expected = var.load(std::memory_order_relaxed);
    int update = expected + addend;
    return var.compare_exchange_weak(expected, update,
std::memory_order_acq_rel, std::memory_order_seq_cst);
}
 
This is asm for armv8-a clang 9.0.0
 
test1(std::atomic<int>, int):
        ldr     w8, [x0]
        ldaxr   w9, [x0]
        cmp     w9, w8
        b.ne    .LBB0_3
        add     w8, w8, w1
        stlxr   w9, w8, [x0]
        cbz     w9, .LBB0_4
        mov     w0, wzr
        ret
.LBB0_3:
        clrex
        mov     w0, wzr
        ret
.LBB0_4:
        mov     w0, #1
        ret
 
I picked a version that just did ll/sc to avoid
the question of whether a failed CASAL did a store or not.
 
I don't see anything that forces a store memory barrier
on all the fail paths.  I could be missing something.

Why would there be one? If the store does not take place, there's no
need for a memory barrier because there's no store for anyone to
synchronize with. The only effect of a failed weak CAS is a load. If
you really need a store on failure because of its side effect you can
always add one.

Andrew.