Re: What do we call non-pipelined designs?

On 12/26/2024 6:57 AM, Thomas Koenig wrote:

Robert Finch <robfi680@gmail.com> schrieb:
 

According to my understanding of  “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.

 Not any more.
 

Non-pipelined
designs perform everything in one long clock cycle.

 Earlier architectures had several clock cycles per instruction,
also without pipelining.  I think the single-clock CPUs mostly
serve as an example for educational purposes.

Yeah. I would have figured N clock cycles per instruction.
For things where speed doesn't really matter, it is cheaper and simpler to burn N cycles and just let signals propagate as they will, moving on to the next item once N cycles have gone by and the task has completed.
Some amount of my audio hardware designs also work this way, as the hardware doesn't need to work too hard to do kHz audio updates on a 50MHz clock.
The graphics hardware uses a fixed latency, but here the data being fetched/processed is a certain number of cycles ahead of the pixel being output.
For sake of higher-res modes, there was a thing of running the main logic 2 pixels at a time and then using posedge/negedge to drive the pixel outputs at twice the effective clock frequency (say, for 1024 or 1280 pixel horizontal resolution).
Though, a bigger limiting factor here is memory bandwidth, and higher res monochrome or Bayer pattern output isn't great...