Re: What do we call non-pipelined designs?

On Thu, 26 Dec 2024 18:54:42 +0000, EricP wrote:

Thomas Koenig wrote:

Robert Finch <robfi680@gmail.com> schrieb:
>

According to my understanding of  “pipelined” most designs are
pipelined. There are not very many non-pipelined designs.

>
Not any more.
>

Non-pipelined
designs perform everything in one long clock cycle.

>
Earlier architectures had several clock cycles per instruction,
also without pipelining.  I think the single-clock CPUs mostly
serve as an example for educational purposes.

>
It is possible to do everything for a risc style ISA in one clock but

??? LDs in 1 cycle
??? IMUL in 1 cycle
??? IDIV in 1 cycle
??? L1 miss in 1 cycle
??? FP <any> in 1 cycle

it would need a Harvard architecture with separate instruction and
data memory because it would have to read the instruction memory and
also LD [reg]->reg or ST reg->[reg] data memory within the same clock.
>
So the only flip-flops would be in the 3-port register file and
the RIP register, and everything between instruction read and result
write is combinatorial logic. The critical timing path would be
2x the mem access time plus combinatorial logic.