Re: Interview with Power's chief designer

Michael S <already5chosen@yahoo.com> schrieb:

On Sun, 29 Dec 2024 01:58:52 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:
>

On Fri, 27 Dec 2024 13:29:22 +0000, Thomas Koenig wrote:
 

Not sure how many of you read Chips and Cheese, but in case you're
interested: Here is an inteview with IBM Power's chief designer,
Bill Starke:
>
https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/
>
There is a lot of talk on OMI (he really doesn't like DDR, and gives
reasons, especially the amount of memory and reliability), plus some
detail on POWER11, which apparently will be a microarchitectural
evolution, but no new ISA parts, and the philosophy behind the
chiplet design they are about to do for the next generation after
that. 

 
He makes a compelling point that DDR is using too many pins and
still does not provide the desired BW available for that number
pf pins. And that a SEREDS interface to DRAMs provide easier to
achieve signaling and larger memories at the same time--similar
to what CXL:memory is attempting.
 

>
Unlike CXL:memory, OMI is not layered on top PCIe gen5 phy.
They claim the same bandwidth with lower latency and lower power.

Interestingly enogh (I only found this when looking)
OMI appears to have been absorbed by CXL.

You can find the OpenCAPI specs, which OMI is based on, at
https://computeexpresslink.org/resource/opencapi-specification-archive/

I don't know where to looks for details of physical layer of OMI, but
would suspect that it is more like HyperTransport or Intel QPI/UPI than
like PCIe. I.e. timing, including phase, is not recovered independently
from every data lane, but provided as a dedicated signal. Likely one
timing signal per group of 4  or 5 data signals.
All above are my speculations not based on knowledge.

If you're so inclined, you can wade through the specs, but it's
likely a non-trivial amount of work...