Re: Interview with Power's chief designer

Michael S <already5chosen@yahoo.com> schrieb:

On Fri, 27 Dec 2024 13:29:22 -0000 (UTC)
Thomas Koenig <tkoenig@netcologne.de> wrote:
>

Not sure how many of you read Chips and Cheese, but in case you're
interested: Here is an inteview with IBM Power's chief designer,
Bill Starke:
 
https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/
 

>
Why no editing?
Why do I have to see 100 repetitions of "you know" ?

It probably took you longer to write that complaint than to read
over all of these :-)

And, BTW, Danish blue is a poor substitute for Roquefort. Even Pecorino
blue is better.
>

There is a lot of talk on OMI (he really doesn't like DDR, and gives
reasons, especially the amount of memory and reliability),

>
I didn't understand this part. My understanding of Power10 and supposed
of Power11 memory architecture is that ideologically it is the same as
Intel'a Beckton and Westmere-EX of early 2010s.

BTW, some more searching turned up https://opencapi.github.io/omi-doc/ .

Of course, everything
is beefier than it was then - there are more links and each link runs
4x to 5x faster than on Beckton. But basic principle is the same, what
Intel called Buffers-on-Board (BoB). I.e. fast link runs from CPU
through either PCB or possibly cable to distance of 1-3 cm from where
they place memory. At this point the is a buffer chip that translates
fast protocol to several industry-standard DDR buses. In Intel's case
there were 2 buses. In POWER10 cases probably 3 or 4.

Power10 has 16 OMI links per SCM (which is the smallest unit, containing
10, 12 or 15 cores), driven by eight on-chip memory controllers.
IBM claims a maximum bandwidth of 409 GB/s per SCM.

You need fewer pins and lower power on your main CPU with that
approach, and can get thus access more DIMMs in parallel.

Buffers used by
Power10 supposedly supported both DDR4 and DDR5. I would expect that
DDR5 is the only remaining option for POWER11.

The CPU doesn't care what is on the other side, that is the beauty
of it.

But the point is that behind the buffer chips they have the same DIMMs
as everybody else with the same poor edge connectors that cause the same
signal integrity and reliability problems.

One important point appears to be that the DDR protocol needs
to be run over shorter wires.  Also, it seems they ECC checks,
error correction and even isolation of flaky units for high
reliability.