Re: the 286, Byte ordering

On Sun, 5 Jan 2025 2:56:08 +0000, John Levine wrote:

According to Anton Ertl <anton@mips.complang.tuwien.ac.at>:

antispam@fricas.org (Waldek Hebisch) writes:

From my point of view main drawbacks of 286 is poor support for
large arrays and problem for Lisp-like system which have a lot
of small data structures and traverse then via pointers.

>
Yes.  In the first case the segments are too small, in the latter case
there are too few segments (if you have one segment per object).

>
Intel clearly had some strong opinions about how people would program
the 286, which turned out to bear almost no relation to the way we
actually wanted to program it.

Clearly, Intel thought that .text, .data, .stack, and .heap were
about all anyone would ever need.

Some of the stuff they did was just perverse, like putting flag
bits in the low part of the segment number rather than the high
bit.  If you had objects bigger than 64K, you had to shift
the segment number three bits to the left when computing
addresses.

Let us just agree that whatever they were thinking, they blew it.

They also apparently didn't expect people to switch segments much.

Clearly. They expected segments to be essentially stagnant--unlike
the people trying to do things with x86s...

If you loaded a segment register with the value it already contained,
it still fetched all of the stuff from memory.

If segment LD was 1 cycle, the number of segment changes would be
fine. But since LDing a segment was so expensive, they probably
could not afford the transistors and wires to do what you suggest.

                                                How many gates would
it have taken to check for the same value and bypass the loads?

286:: 180 gates per segment register
386:: 360 gates per segment register

                                                                If
they had done that, we could have used large model calls everywhere
since long and short calls would be about the same speed, and not
had to screw around deciding what was a long call and what was short
and writing glue codes to allow both kinds.

If you had 32 segment registers, it probably would not have mattered
that segment LD was slow. And if you had 32 pointing registers, you
would not have need a LD-OP ISA.
Sigh ...