Re: Microarchitectural support for counting

Paul A. Clayton wrote:

On 1/3/25 12:24 PM, Scott Lurndal wrote:

EricP <ThatWouldBeTelling@thevillage.com> writes:

[snip]

For MMIO device registers I think having an explicit SPCB instruction
might be better than putting a "no-speculate" flag on the PTE for the
device register address as that flag would be difficult to propagate
backwards from address translate to all the parts of the core that
we might have to sync with.

>
MMIO accesses are, by definition, non-cachable, which is typically
designated in either a translation table entry or associated
attribute registers (MTTR, MAIR).    Non-cacheable accesses
are not speculatively executed, which provides the
correct semantics for device registers which have side effects
on read accesses.

 It is not clear to me that Memory-Mapped I/O requires
non-cacheable accesses. Some addresses within I/O device
address areas do not have access side effects. I would **GUESS**
that most I/O addresses do not have read side effects.

And you would be wrong, at least back in the "old days" when I wrote drivers for some such devices.
The worst was probably the EGA text/graphics adapter which had a bunch of write-only ports, making it completely impossible to context switch.
Even IBM realized this so it was shortly after (1-2 years?) replaced by the VGA adapter which did allow you to query the current status.
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"