Re: stack sizes, Segments

scott@slp53.sl.home (Scott Lurndal) writes:

Well, it gave them a couple scratch registers for use as
kernel and user-mode thread specific region pointers (fs, gs).
>
However, I doubt that played a huge factor in AMD keeping what's
left of 80286 segments, they could have just re-used the
encodings for FS and GS for new GPRs and reserved them for
TLS in ABI's for implementations that support threads.

Unfortunately, Mitch Alsup has not stated the reasoning behind their
decisions, but my speculation why they decided on the current solution
and not on what you outline is:

* The hardware needs a 32+32+32+32-bit (i.e., four-input) adder in the
  address path for IA-32 anyway, and at least a three-input
  64+64+32-bit adder for AMD64, so the additional cost of requiring a
  64+64+64+32-bit adder for AMD64 is relatively small.

* Also, decoding the FS:/GS: prefix as a segment prefix in IA-32 and
  as a GPR (for which register use in the instruction?) in AMD64
  complicates the decoder.

* On the software side, having FS: as separate argument means that
  software can use the full power of the addressing modes to access
  TLS; however, thinking about usage scenarios (arrays in TLS), it
  seems to me that the TLS-base would often be a constant (fitting in
  the regular addressing modes), or is fetched from TLS (which can be
  done with three-address operations) and then used (which also does
  not need segment prefix if the fetched address is absolute rather
  than TLS-relative; and why should it be TLS-relative when the
  address is thread-specific rather than useful across threads).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>