Re: DRAM Chiplet for L3 cache?

On 1/27/2025 1:48 PM, Michael S wrote:

On Mon, 27 Jan 2025 17:18:29 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
 

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:

This brings up the question of why, at least so far, no one is using
a DRAM chiplet (i.e. one made with a DRAM specialized technology),
for the L3 cache.  ISTM that the advantage of being able to put a
much higher capacity cache in the same physical size chiplet is
substantial.

>
There used to be eDRAM used for an L4 cache ("Crystall Well") in some
Intel Broadwell and Skylake variants, as well as eDRAM used as L3
cache on Power8.

 In Power7/8/9 eDRAM is a part of proccessor die, so not quite the same
as OP's suggestion.

True, but as the OP, I give him some slack.  I probably wasn't clear.  I had originally intended to mean using a chiplet manufactured on a DRAM process in order to reduce cost per bit, perhaps by using actual existing, though possibly slightly modified commodity DRAM die, not eDRAM.  The article does a good job of explaining why this isn't a good idea.
--
  - Stephen Fuld
(e-mail address disguised to prevent spam)