Re: DRAM Chiplet for L3 cache?

There were at least 3 times when I wanted to use DRAM as cache.
Even refreshing a row every other cycle was insufficient for
any of the test engineers to sign off on being able to properly
test DRAM on a chip containing CPU cores.
I had even gone to the point of designing* and laying out the
DRAM cells, word line drivers, sense amplifiers, and bit-line
prechargers.
(*) SPICE.