Re: Cost of handling misaligned access

On Sun, 2 Feb 2025 22:44:13 +0000, Chris M. Thomasson wrote:

On 2/2/2025 10:51 AM, MitchAlsup1 wrote:

On Sun, 2 Feb 2025 16:45:19 +0000, EricP wrote:

-------------

I don't think there are line straddle consequences for coherence because
there is no ordering guarantees for misaligned accesses.

>
Generally stated as:: Misaligned accesses cannot be considered ATOMIC.

>
Try it on an x86/x64. Straddle a l2 cache line and use it with a LOCK'ed
RMW. It should assert the BUS lock.

Consider this approach when you have a cabinet of slid in servers,
each server having 128 cores, the cabinet being cache coherent,
and the cabinet having 4096 cores.
Can you say "it donna scale" ??