Re: Fun with a Vax, Cost of handling misaligned access

According to EricP  <ThatWouldBeTelling@thevillage.com>:

The MOVTC and MOVTUC instructions had six operands, five
of which were multibyte, and one of which was one byte.
Each of those multibyte operands could cross a page
boundary, so that's 11 pages.

>
MOVTC had 6 operands, one in a register, one address of byte table,
and 4 multibyte operands which could straddle.

According to my VAX Architecture Handbook, the operands were:

 opcode srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, dstlen.rw, dstaddr.ab

The fill.rb was a single byte fill character which could be in memory, the rest all multibyte.

But all of the operands could use indirect addressing, each of which
could cross a page boundary, so that's 12 more pages.

 
Yes, each memory operand could use deferred indirect (register contains the
address of address of operand) and the addresses could be misaligned and
straddle two pages, so that is 5 virtual addresses per memory operand.

That should be 4 virtual addresses per multibyte operand
and 3 addresses for the byte table.

Pretty close, the deferred modes only did one level of indirection.
There were a bunch of flavors, @(R)+ @B(R) @W(R) @L(R) but they were
all single indirect, so it's four for most operands and three for the
fill byte.

The instruction itself could cross a page boundary, two more pages,
for a total of 25.

 
5 operands gives 25 virtual addresses, +2 for the instruction straddle =

I get 4 addresses for the five long operands plus 3 for the fill byte plus two
for the instruction, total of 25.

Double that for the page tables and it's 50.

Yes, because the page table base register for user process P0 space
(the first lowest 1GB) was a *virtual* address in process P1 space
(the second 1GB), and P1 space PTE virtual address was also a *virtual*
address in system S0 space (the third 1GB).
 
(The net result is for VAX to effect a reverse page table walk similar
to Intel's caching the interior PTE nodes on its top down walk,
then checking them in reverse bottom-up order on a TLB miss.)

Right, it also had to look at the PTEs to find the P0 or P1 table pages.

R's,
John
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