Re: Cost of handling misaligned access

On Mon, 3 Feb 2025 21:04:37 +0000, John Levine wrote:

According to Terje Mathisen  <terje.mathisen@tmsw.no>:

48 pages?  What instruction would need that?
>

I've seen it somewhere but dont't remember where:
>
One candidate would be the POLY (spelling?) polynomial evaluator with
all the arguments (indirectly?) loaded from misaligned addresses, all
straddling page bounaries?

>
No, POLY only had three arguments, the argument, the degree, and the
table of multipliers.  The table could be arbitrarily long but the
instruction was restartable, saving the partial result on the stack
and setting the FPD (first part done) flag for when it resumes so it
only had to be able to load one table entry at a time.
>
MOVTC or MOVTUC were the worst, with six arguments, all of which could
have an indirect address and five of which could cross page
boundaries.
>
But it occurs to me that those instructions are also restartable, so
that only a single byte of the source and destination arguments need
to be addressable at a time. There's six possible indirect adddresses
which can cross page boundaries for 12 pages, two lengths and a table
that can cross a page boundary for six more, and the source and
destination and fill, three more, and the instruction, two more.
That's a total of 23 pages, double it for the P0 or P1 page tables,
and it's only 46 pages.
>
That's still kind of a lot.

Basically, VAX taught us why we did not want to do "all that" in
a single instruction; while Intel 432 taught us why we did not bit
aligned decoders (and a lot of other things).