Re: Cost of handling misaligned access

On 2/2/2025 5:43 PM, MitchAlsup1 wrote:

On Sun, 2 Feb 2025 22:44:13 +0000, Chris M. Thomasson wrote:
 

On 2/2/2025 10:51 AM, MitchAlsup1 wrote:

On Sun, 2 Feb 2025 16:45:19 +0000, EricP wrote:

-------------

I don't think there are line straddle consequences for coherence because
there is no ordering guarantees for misaligned accesses.

>
Generally stated as:: Misaligned accesses cannot be considered ATOMIC.

>
Try it on an x86/x64. Straddle a l2 cache line and use it with a LOCK'ed
RMW. It should assert the BUS lock.

 Consider this approach when you have a cabinet of slid in servers,
each server having 128 cores, the cabinet being cache coherent,
and the cabinet having 4096 cores.
 Can you say "it donna scale" ??

One can be crazy and use misaligned addresses with a LOCK'ed RMW all the time. It's a hardcore death wish? Wow. However, there was an interesting "thing" called QPI iirc that would use it to gain so-called remote memory barriers. It was purely experimental, iirc. Then Say, Windows came up with FlushProcessorWriteBuffers API:
https://learn.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-flushprocesswritebuffers
It's akin to some stuff on Linux. Why do I think Windows did this, humm... To support RCU on Windows? It kind of seems so.