Re: Cost of handling misaligned access

On Tue, 4 Feb 2025 10:09:09 +0000, Anton Ertl wrote:

something along the lines of:

>
uload:
//       addi    a5,a0,7         // unnecessary
        andi    a4,a0,-8
//       andi    a5,a5,-8        // unnecessary
        ld      a2,8(a4)        // load higher
        ld      a3,0(a4)        // load lower
        neg     a4,a0
        andi    a4,a4,7
        andi    a0,a0,7
        slliw   a4,a4,3
        slliw   a5,a0,3
        sll     a5,a3,a5
        sra     a0,a2,a4
        or      a0,a0,a5
        ret

uloadD:
          and     r2,[r1],#-7
          ldd     r3,[r2,0]
          ldd     r4,[r2,8]
          srl     r5,r1,<3,0>      // r1[2..0]
          sll     r5,r5,#3
          carry   r3,{{o}{i}}
          sll     r3,r3,r5
          sll     r1,r4,r5
          ret

>
Fewer instructions, and also a better distribution between various
functional units.
>
IIRC it's only three instructions on MIPS and five instructions on
Alpha, but they have special instructions for this case, because they
were designed for it, whereas RISC-V was designed to have unaligned
accesses.
>
- anton