Top of the PCIe tree

Let us consider a device down on the PCIe tree and it sends up a
DMA request. The device can manage a large number of outstanding
commands to a single process or to multiple different processes.
{{Same problem for interrupts and ATS requests}}
DMA from device Bus;Device,function arrives at the HostBridge.
What part of the PCIe message identifies which command this
PCIe message is for (since the device can have a large number
of commands outstanding) ?