Re: Cost of handling misaligned access

antispam@fricas.org (Waldek Hebisch) writes:

Concerning SIMD: trouble here is increasing vector length and
consequently increasing alignment requirements.

That is not a necessary consequence, on the contrary: alignment
requirements based on SIMD granularity is hardware designer lazyness,
but means that SIMD cannot be used for many of the applications where
SIMD without that limitation can be used.

If you want to have alignment checks, then a SIMD instruction should
check for element alignment, not for SIMD alignment.

But the computer architecture trend is clear: General-purpose
computers do not have alignment restrictions; all that had them have
been discontinued; the last one that had them was SPARC.

A lot of SIMD
code is memory-bound and current way of doing misaligned
access leads to worse performance.  So really no good way
to solve this.  In principle set of buffers for 2 cache lines
each and appropriate shifters could give optimal troughput,
but probably would lead to increased latency.

AFAIK that's what current microarchitectures do, and in many cases
with small penalties for unaligned accesses; see
https://www.complang.tuwien.ac.at/anton/unaligned-stores/

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>