Sujet : Re: Stacks, was Segments
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.archDate : 09. Feb 2025, 22:03:15
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <11e171425c30ac125629c0b2ff600979@www.novabbs.org>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
User-Agent : Rocksolid Light
On Sun, 9 Feb 2025 20:45:13 +0000, EricP wrote:
MitchAlsup1 wrote:
On Thu, 6 Feb 2025 21:53:27 +0000, EricP wrote:
>
Stephen Fuld wrote:
-----------------
>
I am a little confused here. When you talk about I0MMU addresses, are
you talking about memory addresses or disk addresses? ISTM that
protecting memory of lower privileged programs is useless if a higher
privileged program can force a page out to disk, then can read the data
from the disk drive itself. Of course, the same is true for data
written to disk by a lesser privileged program. If the higher
privileged program can read the file, then it can compromise security.
>
I'm just kinda free associating what the consequences of restricting
the HV's access to lesser privilege levels might be.
>
As I understand it, the AMD secure HV approach is that memory owned by a
guest kernel and its applications is encrypted and only the guest kernel
has the key. Memory content is only decrypted while inside the core.
As the key is only stored inside that guest kernel memory there is
no way for HV to get at it.
>
Interesting, so you can see the data you just can't interpret the
bit-patterns. This still leaves the door open for malicious action.
>
Yes. Their Secure VM sounds exactly like what a timeshare vendor might
want
if they desire to sell services to governments and businesses that have
secrets that rogue operators must provably not access.
Just enough to gain the confidence of *.gov buyers, without enough
to prevent NSA from using the data.
Also blocks accidental leaks between guests so you could have multiple
such secure guest OS on the same host.
>
So it doesn't matter that the HV has access to guest memory because it
can only see encrypted memory values. Presumably such data is encrypted
on disk so intercepting a DMA gives you nothing.
>
It maters if HV can access (especially modify) what is in storage
(not memory), making it impossible for secure process from using
his own data !
>
Yes a rogue or buggy HV could DoS a guest OS by scrambling its data.
Or an ECC memory error on critical memory location, like the key.
>
But it doesn't look like blocking HV access to the guest kernel, user,
or sandbox memory accomplishes the same security because the HV can
always diddle its own page tables to grant itself access.
>
My 66000 does it differently. HV can create a PTE that translates
"anywhere", but cannot use the VA of Guest OS or SM in order to
use that PTE. There are 4 VAS privilege levels::
>
HoB = 0 nest HoB = 1 nest
application: application VAS yes no access X
Guest OS application VAS yes Guest OS VAS yes
HyperVisor HyperVisor VAS no Guest OS VAS yes
Secure HyperVisor VAS no SM VAS no
>
So, HV has no 'direct' path to Application VAS using standard
memory access protocols.
>
But the physical memory in use by that guest can be remapped
by rogue HV to be in its own virtual space and then accessed.
You can never get away from the notion that the code creating
PTP and PTE bit patterns, or manipulating Root pointers requires
a certain amount of trust.
Date | Sujet | # | | Auteur |
1 Oct 24 | Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 387 | | MitchAlsup1 |
1 Oct 24 |  Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 386 | | Thomas Koenig |
1 Oct 24 |   Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 379 | | MitchAlsup1 |
2 Oct 24 |    Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 377 | | Brett |
3 Oct 24 |     Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 376 | | Lawrence D'Oliveiro |
3 Oct 24 |      Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Brett |
3 Oct 24 |      Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Anton Ertl |
3 Oct 24 |      Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 373 | | David Brown |
3 Oct 24 |       Byte ordering (was: Whether something is RISC or not) | 372 | | Anton Ertl |
3 Oct 24 |        Re: Byte ordering (was: Whether something is RISC or not) | 1 | | David Brown |
3 Oct 24 |        Re: Byte ordering (was: Whether something is RISC or not) | 369 | | Lawrence D'Oliveiro |
4 Oct 24 |         Re: Byte ordering | 1 | | Lynn Wheeler |
4 Oct 24 |         Re: Byte ordering (was: Whether something is RISC or not) | 365 | | David Brown |
4 Oct 24 |          Re: Byte ordering (was: Whether something is RISC or not) | 364 | | Anton Ertl |
4 Oct 24 |           Re: Byte ordering | 5 | | BGB |
5 Oct 24 |            Re: Byte ordering | 4 | | MitchAlsup1 |
5 Oct 24 |             Re: Byte ordering | 2 | | BGB |
5 Oct 24 |              Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 |             Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
5 Oct 24 |           Re: Byte ordering (was: Whether something is RISC or not) | 13 | | Lawrence D'Oliveiro |
5 Oct 24 |            Re: Byte ordering (was: Whether something is RISC or not) | 12 | | Brett |
5 Oct 24 |             Re: Byte ordering (was: Whether something is RISC or not) | 11 | | Anton Ertl |
5 Oct 24 |              Re: Byte ordering (was: Whether something is RISC or not) | 10 | | Michael S |
6 Oct 24 |               Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 |               Re: Byte ordering (was: Whether something is RISC or not) | 8 | | Brett |
7 Oct 24 |                Re: Byte ordering (was: Whether something is RISC or not) | 7 | | Lawrence D'Oliveiro |
7 Oct 24 |                 Re: Byte ordering (was: Whether something is RISC or not) | 6 | | Brett |
7 Oct 24 |                  Re: Byte ordering (was: Whether something is RISC or not) | 5 | | Michael S |
7 Oct 24 |                   Re: Byte ordering | 2 | | Stefan Monnier |
7 Oct 24 |                    Re: Byte ordering | 1 | | Michael S |
7 Oct 24 |                   Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Lawrence D'Oliveiro |
8 Oct 24 |                    Re: Byte ordering | 1 | | Terje Mathisen |
6 Oct 24 |           Re: Byte ordering | 345 | | David Brown |
6 Oct 24 |            Re: Byte ordering | 344 | | Anton Ertl |
6 Oct 24 |             Re: Byte ordering | 189 | | John Dallman |
7 Oct 24 |              Re: Byte ordering | 20 | | Lawrence D'Oliveiro |
8 Oct 24 |               Re: Byte ordering | 19 | | John Dallman |
9 Oct 24 |                VMS/NT memory management (was: Byte ordering) | 1 | | Stefan Monnier |
15 Oct 24 |                Re: Byte ordering | 2 | | Lawrence D'Oliveiro |
15 Oct 24 |                 Re: Byte ordering | 1 | | MitchAlsup1 |
15 Oct 24 |                Re: Byte ordering | 15 | | Lawrence D'Oliveiro |
15 Oct 24 |                 Re: Byte ordering | 3 | | Michael S |
15 Oct 24 |                  Re: Byte ordering | 1 | | John Dallman |
18 Oct 24 |                  Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
15 Oct 24 |                 Re: Byte ordering | 9 | | John Dallman |
16 Oct 24 |                  Re: Byte ordering | 7 | | George Neuner |
16 Oct 24 |                   Re: Byte ordering | 6 | | Terje Mathisen |
16 Oct 24 |                    Re: Byte ordering | 5 | | David Brown |
17 Oct 24 |                     Re: Byte ordering | 2 | | George Neuner |
17 Oct 24 |                      Re: Byte ordering | 1 | | David Brown |
17 Oct 24 |                     Re: clouds, not Byte ordering | 2 | | John Levine |
17 Oct 24 |                      Re: clouds, not Byte ordering | 1 | | David Brown |
18 Oct 24 |                  Re: Byte ordering | 1 | | Lawrence D'Oliveiro |
16 Oct 24 |                 Re: Byte ordering | 2 | | Paul A. Clayton |
18 Oct 24 |                  Re: Microkernels & Capabilities (was Re: Byte ordering) | 1 | | Lawrence D'Oliveiro |
7 Oct 24 |              80286 protected mode | 168 | | Anton Ertl |
7 Oct 24 |               Re: 80286 protected mode | 5 | | Lars Poulsen |
7 Oct 24 |                Re: 80286 protected mode | 4 | | Terje Mathisen |
7 Oct 24 |                 Re: 80286 protected mode | 1 | | Michael S |
7 Oct 24 |                 Re: 80286 protected mode | 2 | | Lawrence D'Oliveiro |
8 Oct 24 |                  Re: 80286 protected mode | 1 | | Terje Mathisen |
7 Oct 24 |               Re: 80286 protected mode | 3 | | Brett |
7 Oct 24 |                Re: 80286 protected mode | 2 | | Michael S |
7 Oct 24 |                 Re: 80286 protected mode | 1 | | Brett |
7 Oct 24 |               Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 |               Re: 80286 protected mode | 152 | | MitchAlsup1 |
8 Oct 24 |                Re: 80286 protected mode | 4 | | Lawrence D'Oliveiro |
8 Oct 24 |                 Re: 80286 protected mode | 3 | | MitchAlsup1 |
9 Oct 24 |                  Re: 80286 protected mode | 1 | | David Brown |
15 Oct 24 |                  Re: 80286 protected mode | 1 | | Lawrence D'Oliveiro |
8 Oct 24 |                Re: 80286 protected mode | 147 | | Anton Ertl |
8 Oct 24 |                 Re: 80286 protected mode | 1 | | Robert Finch |
9 Oct 24 |                 Re: 80286 protected mode | 145 | | David Brown |
9 Oct 24 |                  Re: 80286 protected mode | 79 | | MitchAlsup1 |
9 Oct 24 |                   Re: 80286 protected mode | 78 | | David Brown |
9 Oct 24 |                    Re: 80286 protected mode | 77 | | Stephen Fuld |
10 Oct 24 |                     Re: 80286 protected mode | 2 | | MitchAlsup1 |
10 Oct 24 |                      Re: 80286 protected mode | 1 | | David Brown |
10 Oct 24 |                     Re: 80286 protected mode | 1 | | David Brown |
11 Oct 24 |                     Re: 80286 protected mode | 73 | | Tim Rentsch |
15 Oct 24 |                      Re: 80286 protected mode | 72 | | Stefan Monnier |
15 Oct 24 |                       Re: 80286 protected mode | 30 | | MitchAlsup1 |
16 Oct 24 |                        Re: 80286 protected mode | 25 | | MitchAlsup1 |
16 Oct 24 |                         Re: C and turtles, 80286 protected mode | 13 | | John Levine |
16 Oct 24 |                          Re: C and turtles, 80286 protected mode | 7 | | MitchAlsup1 |
16 Oct 24 |                           Re: C and turtles, 80286 protected mode | 6 | | John Levine |
17 Oct 24 |                            Re: C and turtles, 80286 protected mode | 5 | | Thomas Koenig |
20 Oct 24 |                             Re: C and turtles, 80286 protected mode | 4 | | Lawrence D'Oliveiro |
20 Oct 24 |                              Re: C and turtles, 80286 protected mode | 3 | | George Neuner |
22 Oct 24 |                               Re: C and turtles, 80286 protected mode | 2 | | Tim Rentsch |
22 Oct 24 |                                Re: C and turtles, 80286 protected mode | 1 | | George Neuner |
16 Oct 24 |                          Re: C and turtles, 80286 protected mode | 1 | | David Brown |
16 Oct 24 |                          Re: C and turtles, 80286 protected mode | 4 | | Paul A. Clayton |
17 Oct 24 |                           Re: C and turtles, 80286 protected mode | 1 | | David Brown |
20 Oct 24 |                           Re: C and turtles, 80286 protected mode | 2 | | Lawrence D'Oliveiro |
20 Oct 24 |                            Re: C and turtles, 80286 protected mode | 1 | | Paul A. Clayton |
16 Oct 24 |                         Re: 80286 protected mode | 7 | | Thomas Koenig |
16 Oct 24 |                          Re: 80286 protected mode | 2 | | MitchAlsup1 |
17 Oct 24 |                           Re: 80286 protected mode | 1 | | Tim Rentsch |
17 Oct 24 |                          Re: 80286 protected mode | 4 | | Tim Rentsch |
17 Oct 24 |                           Re: fine points of dynamic memory allocation, not 80286 protected mode | 3 | | John Levine |
17 Oct 24 |                         Re: 80286 protected mode | 3 | | George Neuner |
17 Oct 24 |                         Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 |                        Re: 80286 protected mode | 3 | | David Brown |
17 Oct 24 |                        Re: 80286 protected mode | 1 | | Tim Rentsch |
16 Oct 24 |                       Re: 80286 protected mode | 41 | | David Brown |
9 Oct 24 |                  Re: 80286 protected mode | 51 | | Thomas Koenig |
13 Oct 24 |                  Re: 80286 protected mode | 14 | | Anton Ertl |
8 Oct 24 |               Re: 80286 protected mode | 6 | | John Levine |
3 Jan 25 |             Re: Byte ordering | 154 | | Waldek Hebisch |
6 Oct 24 |         Re: Byte ordering (was: Whether something is RISC or not) | 2 | | Michael S |
3 Oct 24 |        Re: Byte ordering (was: Whether something is RISC or not) | 1 | | John Dallman |
2 Oct 24 |    Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Thomas Koenig |
2 Oct 24 |   Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 5 | | David Schultz |
3 Oct 24 |   Re: Whether something is RISC or not (Re: PDP-8 theology, not Concertina II Progress) | 1 | | Lawrence D'Oliveiro |