BGB <cr88192@gmail.com> wrote:[snip]
Yes, LSL 1 can be implemented by ADD, but LSR/ASR 1 needs a dedicatedThe smallest cores I had managed had used a simplified SH-based design:You mean no variable shift, or no large shifts, you have to support divide
Fixed-length 16 bit instructions, with 16 registers;
Only (Reg) and (Reg, R0) addressing;
Aligned only;
No shift or multiply;
by 2, right?
instruction, right?
IIRC the SuperH has some power-of-two shift instructions, e.g:
shlr Rn
shlr2 Rn
shlr4 Rn
shlr8 Rn
shlr16 Rn
It takes up some encoding space and costs extra cycles/instructions to
do a full shift (e.g. 7=4+2+1), but I guess you can make relatively
cheap shift hardware that way? Maybe you can get away with even fewer
instructions (e.g. only 1, 4, 16)?
| Date | Sujet | # | Auteur | |
| 3 Feb 25 |  Re: Cost of handling misaligned access | 106 | Anton Ertl |
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