Re: Cost of handling misaligned access

Say, one could imagine an abstract model where Binary64 FADD works sort
of like:
   sgnA=valA>>63;
   sgnB=valA>>63;
   expA=(valA>>52)&2047;
   expB=(valB>>52)&2047;
   fraA=(valA&((1ULL<<52)-1));
   fraB=(valB&((1ULL<<52)-1));
   if(expA!=0)fraA|=1ULL<<52;
   if(expB!=0)fraB|=1ULL<<52;
   fraA=fraA<<9;  //9 sub ULP bits
   fraB=fraB<<9;
   shrA=(expB>=expA)?(expB-expA):0;
   shrB=(expA>=expB)?(expA-expA):0;

   sgn2A=sgnA; exp2A=expA; fra2A=fraA>>shrA;
   sgn2B=sgnB; exp2B=expB; fra2B=fraB>>shrB;
   //logical clock-edge here.
   fr1C_A=fra2A+fra2B;
   fr1C_B=fra2A-fra2B;
   fr1C_C=fra2B-fra2A;
   if(sgn2A^sgn2B)
   {
     if(fr1C_C>>63)
       { sgn1C=sgn2A; fra1C=fr1C_B; }
     else
       { sgn1C=sgn2B; fra1C=fr1C_C; }
   }
   else
     { sgn1C=!sgn2A; fra1C=fr1C_A; }
   //logical clock-edge here.
   if(fra2C>>62)
     { exp3C=exp2C+1; fra3C=fra2C>>1; }
   else
     { shl=clz64(fra2C)-2; exp3C=exp2C-shl; fra3C=fra2C<<shl; }
   //logical clock-edge here.
   if((exp3C>=2047) || (exp3C<=0))
     { sgnC=sgn2C; expC=(exp3C<=0)?0:2047; fraC=0; }
   else
   {
     sgnC=sgn2C; expC=exp3C; fraC=fra3C>>9;
     //if rounding is done, it goes here.
   }
   valC=(sgnC<<63)|(expC<<52)|fraC;
   //final clock edge.
   //result is now ready.