Re: Cost of handling misaligned access

But, for a 64-bit adder, still basically need to give it a clock-cycle to do its thing. Though, not like 32 is particularly fast either; hence part of the whole 2 cycle latency on ALU ops thing. Mostly has to do with ADD/SUB (and CMP, which is based on SUB).

  Admittedly part of why I have such mixed feelings on full compare-and- branch:
   Pro: It can offer a performance advantage (in terms of per-clock);
   Con: Branch is now beholden to the latency of a Subtract.
 

CMP can be implemented without a SUB using the '<' and '>' operators which I think work left to right. It should give a little better timing.
I have not found the compare-and-branch operation to be on the critical timing path.