Re: Cost of handling misaligned access

On 2025-02-21 4:47 p.m., BGB wrote:

On 2/21/2025 1:51 PM, EricP wrote:

BGB wrote:

>

The 75MHz was mostly experimental, mostly I am running at 50MHz because it is easier (a whole lot of corners need to be cut for 75MHz, so often overall performance ended up being worse).
  

<snip>

As for Virtex: I am not made of money...
 Virtex tends to be absurdly expensive high-end FPGAs.
   Even the older Virtex chips are still absurdly expensive.
  Kintex is considered mid range, but still too expensive, and mostly not usable in the free versions of Vivado (and there are no real viable FOSS alternatives to Vivado). When I tried looking at some of the "open source" tools for targeting Xilinx chips, they were doing the hacky thing of basically invoking Xilinx's tools in the background (which, if used to target a Kintex, is essentially piracy).
 Where, a valid FOSS tool would need to be able to do everything and generate the bitstream itself.
   Mostly I am using Spartan-7 and Artix-7.
   Generally at the -1 speed grade (slowest, but cheapest).
 These are mostly considered low-end and consumer-electronics oriented FPGAs by Xilinx.
  Or, by "car analogies":
You can't expect a "VW Jetta" to perform like a "Ferrari Enzo" even if the "Jetta" is a newer model year...
   Cheapest FPGA dev-boards I have gotten a (minimal) BJX2 core onto were around $70 (XC7S25). Most expensive dev-board I have is the Nexys A7 (XC7A100T), but it has gone up in price (IIRC, it was around $290 at the time; right now seems like $350, but was IIRC a bit more in 2021/2022).
  There was the temptation to get a "Nexys Video", which an XC7A200T-2, but, very expensive (around $600 IIRC). However, this chip *could* pass 75MHz a bit more easily (though, still not enough to easily reach 100MHz).
  I have a QMTech board with an XC7A200T at -1, but generally, it seems to actually have a slightly harder time passing timing constraints than the XC7A100T in the Nexys A7 (possibly some sort of Vivado magic here).
  Generally, also hard to find FPGA boards much under $100 that "aren't crap".
 A lot of the ICE40 boards fail on both, often not really any cheaper than XC7S25 or XC7A35T based boards, but much worse in comparison.
 There was rumor of cheaper boards (in the $30-$50 range), but not seen anything that seems worth bothering with in this range.
 

For me, it was either get a board with greater capacity or find a new hobby. I tried to distract myself for a while by playing with the trainset or writing. But ultimately I decided to blow a fair chunk of change on a Kintex-320. I am expecting the board to last me a number of years. Cost per year is not too bad. Higher capacity chips are naturally more expensive.
I have a four-wide machine implemented on it, running at 40MHz (the machine can perform a max of eight ops per cycle). Of course, I have not got the machine to work in an FPGA yet, although it works in SIM. I am still playing with the ISA some so have not put a lot of effort into FPGA.
Latest work is in routing outputs of functional units to the register file. I plan on using small queues for this with the goal of having only four write ports when there may be six or eight functional units outputting results.
Some instructions manipulate 128-bit values, which ATM requires two write ports for updates.

 

and this does 64-bit ADD up to 428 MHz (2.3 ns) on a Virtex-6:
>
Fast and Area Efficient Adder for Wide Data in Recent Xilinx FPGAs, 2016
http://www.diva-portal.org/smash/get/diva2:967655/FULLTEXT02.pdf
>

 Errm, skim, this doesn't really look like something you can pull off in normal Verilog.
 Generally, one doesn't control over how the components hook together, only one can influence what happens based on how they write their Verilog.
 You can just write:
   reg[63:0] tValA;
   reg[63:0] tValB;
   reg[63:0] tValC;
   tValC=tValA+tValB;