Re: Cost of handling misaligned access

On 2025-02-22 5:18 p.m., EricP wrote:

Robert Finch wrote:

On 2025-02-22 10:16 a.m., EricP wrote:

BGB wrote:

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Generally, Vivado synthesis seems to mostly be happy (at 50 MHz), if the total logic path length stays under around 12 or so. Paths with 15 or more are often near the edge of failing timing.
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At 75MHz, one has to battle with pretty much anything much over 8.
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And, at 200MHz, you have have path lengths of 2 that are failing...
Like, it seemingly can't do much more than "FF -> LUT -> FF" at these speeds.

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This can't just be left to the random luck of the wire router.
There must be something else that these commercial and academic users
are able to do to reliably optimize their design.
Maybe its a tool only available to big bucks customers.
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This has me curious. I'm going to keep looking around.
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I am sure it can be done as I have seen a lot of papers too with results in the hundreds of megahertz. It has got to be the manual placement and routing that helps. The routing in my design typically takes up about 80% of the delay. One can build circuits up out of individual primitive gates in Verilog (or(), and(), etc) but for behavioral purposes I do not do that, instead relying on the tools to generate the best combinations of gates. It is a ton of work to do everything manually. I am happy to have things work at 40 MHz even though 200 MHz may be possible with 10x the work put into it. Typically running behavioural code. Doing things mostly for my own edification. ( I have got my memory controller working at 200 MHz, so it is possible).
One thing that I have found that helps is to use smaller modules and tasks for repetitive code where possible. The tools seem to put together a faster design if everything is smaller modules. I ponder it may have to do with making place and route easier.

 I downloaded a bunch of Vivado User Guides PDF's from AMD/Xilinx.
They say it can be done. It seems to be done with "constraints" files,
assigning properties to the devices and netlists,
defining relative placement macros, etc.
 It sounds like one can optimize a module independently, what they call
Out Of Context (OOC), then checkpoint that module design and reload it.
 For BGB it might be sufficient to just optimize the ALU from 2 to 1 clock,
checkpoint that module design, and that might lower his synthesis time
and double his ALU performance.
  From:
UG892 Vivado Design Suite User Guide Design Flows Overview 2024-11-13
 "Hierarchical Design
Hierarchical Design (HD) flows enable you to partition a design into smaller,
more manageable modules to be processed independently. The hierarchical
design flow involves proper module interface design, constraint definition,
floorplanning, and some special commands and design techniques.
 Using a modular approach to the hierarchical design lets you analyze modules
independent of the rest of the design, and reuse modules in the top-down
design. A team of users can iterate on specific sections of a design,
achieving timing closure and other design goals, and reuse the results.
 There are several Vivado features that enable a hierarchical design approach,
such as the synthesis of a logic module outside of the context (OOC) of the
top-level design. You can select specific modules, or levels of the design
hierarchy, and synthesize them OOC. Module-level constraints can be applied
to optimize and validate module performance. The module design checkpoint
(DCP) will then be applied during implementation to build the top-level
netlist. This method can help reduce top-level synthesis runtime, and
eliminate re-synthesis of completed modules."
 I haven't found just how to do it yet as the info appears to be spread
across multiple documents. Some relevant ones may be:
 UG903 Vivado Design Suite User Guide Using Constraints 2024-12-20
UG904 Vivado Design Suite User Guide Implementation 2024-11-14
UG905 Vivado Design Suite User Guide Hierarchical Design OBSOLETE 2023-10-18
UG906 Vivado Design Suite User Guide Design Analysis and Closure Techniques
       2024-12-19
UG912 Vivado Design Suite User Guide Properties Reference Guide 2024-12-18
    

In Vivado there is an option under the menu IP integrator to create “block designs”, which are OOC designs. I have experimented with it some but found most of the time it would not allow me to create a block design, especially if there are inferred components in the design like RAMs. There is probably a way to get things to work, but not without a lot of rework to my modules.
Vivado also supports incremental synthesis and implementation. If this option is on, the system can build much faster as it skips over parts that have already been done. I have found this option does not always seem to work though, so I usually have it turned off. The build times for the entire system are about ½ hour for synthesis.
It looks like for the faster 64-bit add carry generate and propagate are calculated for the low order 32-bit then the carry is fed to the upper 32-bits of the adder where a simple ripple carry is used. This makes the add about 35% faster at a cost of a handful of additional LUTs. As I usually run out of LUTs I trade some performance for a smaller core size.