Re: Cost of handling misaligned access

On Tue, 25 Feb 2025 14:20:45 +0000, EricP wrote:

Michael S wrote:

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>
No, I mean florplanning, as well as most other manual physical-level
optimization are not used at all in 99% percents of FPGA designs that
started after year 2005.

>
Is that because the auto place and route got good enough that it is
unnecessary? Or maybe the fpga resources grew enough that autoroute
didn't have to struggle to find optimal positions and paths
(being an optimal packing problem and a traveling salesman problem).

Athlon (1998) used hand place auto-route. So, auto-route has been
good enough since 2000 at latest.

Also BGB mentioned in another thread a while back that he was getting
what sounded like random variation of critical paths from run to run.
That suggests to me the automatic tools may not be properly recognizing
the different modules and produce some non-optimal positions or paths.
So giving it a hint that "this stuff goes together" might help.

Consider the optimizer/place/route thingamabob; and a signal that
crosses from one module to another. The optimizer changes from
a 2-LUT delay to a 1 LUT delay, but now the fan-out of that LUT
doubles, so instead of speeding up, the signal path slows down.

Anyway, it should be testable. Inspect the auto placements module wiring
and if there are any obviously crazy decision then try the placement
tool
an see if the speed improves or critical path variation goes away.