Why VAX Was the Ultimate CISC and Not RISC

Found this paper
<https://gordonbell.azurewebsites.net/Digital/Bell_Retrospective_PDP11_paper_c1998.htm>
at Gordon Bell’s website. Talking about the VAX, which was designed as
the ultimate “kitchen-sink” architecture, with every conceivable
feature to make it easy for compilers (and humans) to generate code,
he explains:

    The VAX was designed to run programs using the same amount of
    memory as they occupied in a PDP-11. The VAX-11/780 memory range
    was 256 Kbytes to 2 Mbytes. Thus, the pressure on the design was
    to have very efficient encoding of programs. Very efficient
    encoding of programs was achieved by having a large number of
    instructions, including those for decimal arithmetic, string
    handling, queue manipulation, and procedure calls. In essence, any
    frequent operation, such as the instruction address calculations,
    was put into the instruction-set. VAX became known as the
    ultimate, Complex (Complete) Instruction Set Computer. The Intel
    x86 architecture followed a similar evolution through various
    address sizes and architectural fads.

The VAX project started roughly around the time the first RISC
concepts were being researched. Could the VAX have been designed as a
RISC architecture to begin with? Because not doing so meant that, just
over a decade later, RISC architectures took over the “real computer”
market and wiped the floor with DEC’s flagship architecture,
performance-wise.

The answer was no, the VAX could not have been done as a RISC
architecture. RISC wasn’t actually price-performance competitive until
the latter 1980s:

    RISC didn’t cross over CISC until 1985. This occurred with the
    availability of large SRAMs that could be used for caches. It
    should be noted at the time the VAX-11/780 was introduced, DRAMs
    were 4 Kbits and the 8 Kbyte cache used 1 Kbits SRAMs. Memory
    sizes continued to improve following Moore’s Law, but it wasn’t
    till 1985, that Reduced Instruction Set Computers could be built
    in a cost-effective fashion using SRAM caches. In essence RISC
    traded off cache memories built from SRAMs for the considerably
    faster, and less expensive Read Only Memories that held the more
    complex instructions of VAX (Bell, 1986).