If you look at the VAX 8800 or NVAX uArch you see that even in 1990 it
was still taking multiple clocks to serially decode each instruction and
that basically stalls away any benefits a pipeline might have given.
How many clocks did Alpha take to process each instruction? Because I
recall the initial chips had clock speeds several times that of the RISC
competition, but performance, while competitive, was not several times
greater.
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